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very low power cmos sram 512k x 8 bit bs62lv4006 r0201-bs62lv4006 revision 1.5 oct. 2008 1 pb-free and green package materials are compliant to rohs ? features y wide v cc operation voltage : 2.4v ~ 5.5v y very low power consumption : v cc = 3.0v operation current : 30ma (max.) at 55ns 2ma (max.) at 1mhz standby current : 2/4ua (max.) at 70/85 o c v cc = 5.0v operation current : 70ma (max.) at 55ns 10ma (max.) at 1mhz standby current : 10/20ua (max.) at 70/85 o c y high speed access time : -55 55ns (max.) at v cc =3.0~5.5v -70 70ns (max.) at v cc =2.7~5.5v y automatic power down when chip is deselected y easy expansion with ce and oe options y three state outputs and ttl compatible y fully static operation y data retention supply voltage as low as 1.5v ? description the bs62lv4006 is a high performance, very low power cmos static random access memory organized as 524,288 by 8 bits and operates form a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and ci rcuit techniques provide both high speed and low power features with maximum cmos standby current of 4/20ua at vcc=3v/5v at 85 o c and maximum access time of 55/70ns. easy memory expansion is provided by an active low chip enable (ce), and active low output enable (oe) and three-state output drivers. the bs62lv4006 has an automatic power down feature, reducing the power consumption significant ly when chip is deselected. the bs62lv4006 is available in dice form, jedec standard 32 pin 450mil plastic sop, 600mil plastic dip, 400 mil tsop ii, 8mmx13.4mm stsop and 8mmx20mm tsop package. ? power consumption power dissipation standby (i ccsb1 , max) operating (i cc , max) v cc =5v v cc =3v product family operating temperature v cc =5.0v v cc =3.0v 1mhz 10mhz f max. 1mhz 10mhz f max. pkg type bs62lv4006dc dice bs62lv4006ec tsop ii-32 bs62lv4006pc pdip-32 bs62lv4006sc sop-32 bs62lv4006stc stsop-32 bs62lv4006tc commercial +0 o c to +70 o c 10ua 2.0ua 9ma 43ma 68ma 1.5ma 18ma 29ma tsop-32 bs62lv4006ei tsop ii-32 bs62lv4006pi pdip-32 bs62lv4006si sop-32 bs62lv4006sti stsop-32 bs62lv4006ti industrial -40 o c to +85 o c 20ua 4.0ua 10ma 45ma 70ma 2ma 20ma 30ma tsop-32 ? pin configurations ? block diagram brilliance semiconductor, inc. reserves the right to change products and specifications without notice. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 g nd vcc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bs62lv4006ec bs62lv4006ei bs62lv4006sc bs62lv4006si bs62lv4006pc bs62lv4006pi ? oe a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 we a17 a15 vcc a18 a16 a14 a12 a7 a6 a5 a4 ? bs62lv4006tc bs62lv4006ti bs62lv4006stc bs62lv4006sti 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 address input buffer row decoder memory array 1024 x 4096 column i/o write driver sense am p column decoder address input buffer a 4 a 3 a 2 a 1 a 0 data input buffer control dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a12 a14 a16 a18 a15 a17 a13 a8 a9 a11 8 8 8 8 9 256 4096 1024 10 a 5 a 7 ce we oe v cc gnd data output buffer a 6 a 0
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 2 ? pin descriptions name function a0-a18 address input these 19 address inputs select one of the 524,288 x 8-bit in the ram ce chip enable input ce is active low. chip enable must be active when data read form or write to the device. if chip enable is not active, the dev ice is deselected and is in standby power mode. the dq pins will be in the high impedanc e state when the device is deselected. we write enable input the write enable input is active low and c ontrols read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, dat a will be present on the dq pins and they will be enabled. the dq pins will be in the high impendence state when oe is inactive. dq0-dq7 data input/output ports there 8 bi-directional ports are used to read data from or write data into the ram. v cc power supply gnd ground ? truth table mode ce we oe i/o operation v cc current not selected (power down) h x x high z i ccsb , i ccsb1 output disabled l h h high z i cc read l h l d out i cc write l l x d in i cc ? absolute maximum ratings (1) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 (2) to 7.0 v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. ?2.0v in case of ac pulse width less than 30 ns. ? operating range rang ambient temperature v cc commercial 0 o c to + 70 o c 2.4v ~ 5.5v industrial -40 o c to + 85 o c 2.4v ~ 5.5v ? capacitance (1) (t a = 25 o c, f = 1.0mhz) symbol pamameter conditions max. units c in input capacitance v in = 0v 6 pf c io input/output capacitance v i/o = 0v 8 pf 1. this parameter is guaranteed and not 100% tested.
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 3 ? dc electrical characteristics (t a = -40 o c to +85 o c) parameter name parameter test conditions min. typ. (1) max. units v cc power supply 2.4 -- 5.5 v v il input low voltage -0.5 (2) -- 0.8 v v ih input high voltage 2.2 -- v cc +0.3 (3) v i il input leakage current v cc = max, v in = 0v to v cc -- -- 1 ua i lo output leakage current v cc = max, ce= v ih , or oe = v ih , v i/o = 0v to v cc -- -- 1 ua v ol output low voltage v cc = max, i ol = 2.0ma -- -- 0.4 v v oh output high voltage v cc = min, i oh = -1.0ma 2.4 -- -- v v cc =3.0v 30 i cc (5) operating power supply current ce = v il , i dq = 0ma, f = f max (4) v cc =5.0v -- -- 70 ma v cc =3.0v 2 i cc1 operating power supply current ce = v il , i dq = 0ma, f = 1mhz v cc =5.0v -- -- 10 ma v cc =3.0v 0.5 i ccsb standby current ? ttl ce = v ih , i dq = 0ma v cc =5.0v -- -- 1.0 ma v cc =3.0v 0.25 4.0 i ccsb1 (6) standby current ? cmos ce R v cc -0.2v, v in R v cc -0.2v or v in Q 0.2v v cc =5.0v -- 1.5 20 ua 1. typical characteristics are at t a =25 o c and not 100% tested. 2. undershoot: -1.0v in case of pulse width less than 20 ns. 3. overshoot: v cc +1.0v in case of pulse width less than 20 ns. 4. f max =1/t rc. 5. i cc (max.) is 29ma/68ma at v cc =3.0v/5.0v and t a =70 o c. 6. i ccsb1(max.) is 2.0ua/10ua at v cc =3.0v/5.0v and t a =70 o c. ? data retention characteristics (t a = -40 o c to +85 o c) symbol parameter test conditions min. typ. (1) max. units v dr v cc for data retention ce R v cc -0.2v, v in R v cc -0.2v or v in Q 0.2v 1.5 -- -- v i ccdr (3) data retention current ce R v cc -0.2v, v in R v cc -0.2v or v in Q 0.2v -- 0.1 1.5 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns 1. v cc =1.5v, t a =25 o c and not 100% tested. 2. t rc = read cycle time. 3. i ccrd(max.) is 1.0ua at t a =70 o c. ? low v cc data retention waveform (1) (ce controlled) data retention mode v cc t cdr v cc t r v ih v ih ce R v cc - 0.2v v dr R 1.5v ce v cc
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 4 ? ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc t clz , t olz , t chz , t ohz , t whz c l = 5pf+1ttl output load others c l = 30pf+1ttl 1. including jig and scope capacitance. ? key to switching waveforms waveform inputs outputs must be steady must be steady may change from ?h? to ?l? will be change from ?h? to ?l? may change from ?l? to ?h? will be change from ?l? to ?h? don?t care any change permitted change : state unknow does not apply center line is high inpedance ?off? state ? ac electrical characteristics (t a = -40 o c to +85 o c) read cycle cycle time : 55ns (v cc = 3.0~5.5v) cycle time : 70ns (v cc = 2.7~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t rc read cycle time 55 -- -- 70 -- -- ns t av q x t aa address access time -- -- 55 -- -- 70 ns t e1lqv t acs chip select access time -- -- 55 -- -- 70 ns t glqv t oe output enable to output valid -- -- 30 -- -- 35 ns t e1lqx t clz chip select to output low z 10 -- -- 10 -- -- ns t glqx t olz output enable to output low z 5 -- -- 5 -- -- ns t e1hqz t chz chip select to output high z -- -- 30 -- -- 35 ns t ghqz t ohz output enable to output high z -- -- 25 -- -- 30 ns t av q x t oh data hold from address change 10 -- -- 10 -- -- ns c l (1) 1 ttl output all input pulses 90% v cc gnd rise time : 1v/ns fall time : 1v/ns 90%
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 5 ? switching waveforms (read cycle) read cycle 1 (1,2,4) read cycle 2 (1,3,4) read cycle 3 (1, 4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. t rc t oh t aa d out address t oh t clz (5) d out ce t a cs t chz (5) t oh t rc t oe d out ce oe address t clz (5) t a cs t chz (1 , 5) t ohz (5) t olz t aa
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 6 ? ac electrical characteristics (t a = -40 o c to +85 o c) write cycle cycle time : 55ns (v cc = 3.0~5.5v) cycle time : 70ns (v cc = 2.7~5.5v) jedec parameter name paraneter name description min. typ. max. min. typ. max. units t avax t wc write cycle time 55 -- -- 70 -- -- ns t e1lwh t cw chip select to end of write 55 -- -- 70 -- -- ns t av w l t as address set up time 0 -- -- 0 -- -- ns t av w h t aw address valid to end of write 55 -- -- 70 -- -- ns t wlwh t wp write pulse width 30 -- -- 35 -- -- ns t whax t wr write recovery time (ce, we) 0 -- -- 0 -- -- ns t wlqz t whz write to output high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 25 -- -- 30 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whqx t ow end of write to output active 5 -- -- 5 -- -- ns ? switching waveforms (write cycle) write cycle 1 (1) t wc t wr (3) t cw (11) t wp (2) t aw t ohz (4 , 10) t as t dh t dw d in d out we ce oe address (5)
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 7 write cycle 2 (1,6) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the out put state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. t wc t cw (11) t wp (2) t aw t whz (4 , 10) t as t dh t dw d in d out we ce t ow (7) (8) (8 , 9) address ( 5 )
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 8 ? ordering information note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described he rein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be exp ected to result in significant injury or death, including life- support systems and critical medical instruments. ? package dimensions package d: dice e: tsop ii p: pdip s: sop t: tsop (8mm x 20mm) st: small tsop (8mm x 13.4mm) bs62lv4006 x x z y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material g: green, rohs compliant p: pb free, rohs compliant base metal with plating c c1 section a-a b1 b sop -32
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 9 ? package dimensions (continued) stsop - 32 tsop - 32
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 10 ? package dimensions (continued) pdip - 32
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 11 ? package dimensions (continued) 3. dimension d does not include mold protrusion. rad r1 0~8 detail "x" rad r with plating base metal section y-y dambar intrusion shall not cause the lead to be narrower be wider than the max b dimension by more than 0.13mm allowable dambar protrusion shall not cause the lead to 4. dimension b does not include dambar protrusions/intrusion. interlead protrusion shall not exceed 0.25(0.01") per side. dimension e1 does not include interlead protrusion. mold protrusion shall not exceed 0.15(0.006") per side. than the min b dimension by more than 0.07mm. 0.20 t x e1 e seating plane y -t- 1 y y 16 "x" 32 -x- 17 0.050 basic 0.8 ref 0.031 ref 0.95 ref 2. refreence document : jedec ms-024 1. controlling dimension : millimeters. y note: r1 zd r l2 0.12 0.12 0.10 0.005 0.005 0.25 0.037 ref 0.25 basic 1.27 basic l1 l e e1 0.40 0.50 10.03 10.16 e d c1 c 11.56 20.82 11.76 20.95 0.10 0.12 0.127 0.016 0.394 0.60 10.29 0.010 basic 0.020 0.400 0.004 0.005 0.455 0.820 11.96 21.08 0.16 0.21 0.463 0.825 0.005 0.004 0.010 0.024 0.405 0.471 0.830 0.006 0.008 dimension nom. b1 b a2 a1 0.30 0.30 0.40 0.95 0.05 1.00 0.10 a min. (mm) 0.012 0.012 0.037 0.002 0.52 0.45 1.05 0.15 0.016 0.039 0.004 min. max. 1.20 nom. (inch) dimension 0.018 0.020 0.042 0.006 max. 0.047 e b zd d a2 a a1 0.44 ref 0.44 ref l1 gage plane l2 l c b b1 c1 c tsop ii - 32
bs62 l v 4006 r0201-bs62lv4006 revision 1.5 oct. 2008 12 ? revision history revision no. history draft date remark 1.2 to add icc1 characteristic parameter jan. 13, 2006 to improve iccsb1 spec. i-grade from 60ua to 20ua at 5.0v 10ua to 4.0ua at 3.0v c-grade from 30ua to 10ua at 5.0v 5.0ua to 2.0ua at 3.0v 1.3 to add 400 mil tsop ii package type march 20, 2006 1.4 change i-grade operation temperature range may. 25, 2006 - from ?25 o c to ?40 o c 1.5 typical value of standby current is replaced by oct. 31, 2008 maximum value in featues and description section remove ?-: normal? (leaded) pkg material in ordering information remove bga package

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